1. 集成電路設計有哪些常用工具,什麼地方可以下載
應用Verilog/VHDL語言進行設計、綜合和物理編譯、系統驗證和布線
可以用MAX-PLUSII軟體
用Synopsys/Avanti等工具分析和優化放大器等
可以去21IC.COM看看
很權威的網站
下載軟體
根據具體軟體名稱
搜索
根據網速的快慢下載吧
2. synopsys 下怎麼使用calibre
首先用搜索引擎或者軟體下載工具搜索calibre並下載。
左鍵雙擊.msi安裝包，進入calibre的安裝向導。
完成之後，點擊finish，並且選中launch calibre。
第一次運行calibre的時候，會有一個歡迎向導，在這個向導中，有幾項內容需要設置。語言和書庫位置。
下面選擇電子書閱讀設備，如果不知道自己的閱讀設備，那就選擇默認就行。
歡迎向導完成之後，可以點擊「在線視頻」看一看calibre的基本使用方法。不過是全英文的。
進入到calibre的主頁面。
可以看看calibre網站的視頻，很有幫助。
3. synopsys軟體下載和安裝
我也在裝
網上好難找啊，您能給我發一下這個軟體嗎？萬分感激
4. verilog編譯軟體synopsys VCS哪裡可以下載
迅雷 哇嘎 漢魅 。。。
5. 請問哪有synopsys DC下載
像這種軟體估計得到專業的EDA論壇，需要注冊外加積分才能下載到。
你有solvnet賬號的話直接去synopsys下吧。
6. 哪裡可以下載到cadence和synopsys的軟體
先學學Linux吧，這些軟體一般在Linux下運行，特別是ic5141這些主流軟體，我也是微電子的，
7. synopsys design compiler哪裡能下到04或05版本
http://p2p.uying.com/html/20060322/19421381139.stm
http://emule.cdp2p.com/Article/sfotware/a2/Article_29508.html
synopsys.Design.Compiler.2000.v5.nt
文名稱：synopsys.Design.Compiler.2000.v5.nt
英文名稱：synopsys.Design.Compiler.2000.v5.nt
資源類型：ISO
版本：2000 for nt
發行時間：2000年
製作發行：synopsys
地區：美國
語言：英語
簡介：
[通過安全測試]
殺毒軟體：symantec
病毒庫：2006-3-15
通過安裝測試]WindowsXP SP2
軟體版權歸原作者及原軟體公司所有，如果你喜歡，請購買正版軟體
這是本軟體windows平台最後一個版本, 最新版本都為unix版.
破解說明:
Synopsys Design Compiler 安裝指南：
1.運行安裝文件，按照提示進行安裝過程。
2.必須安裝scl_1_1_NT，才能使License.dat起作用。
3.把license file的前面兩行改為如下：
SERVER this_host ANY 27000
VENDOR snpslmd D:\scl\msvc50\bin\snpslmd.exe
^^^這是scl（synopsys common license 的安裝目錄）
然後設置環境變數($HOME)。
將License.dat拷貝到 C:\flexlm 目錄下
然後啟動scl（開始->程序->synopsys procts->Synopsys Common License
->flexlm.cpl
設置flexlm.cpl 窗口中的數據.
設置好各項變數，然後找到control-》start啟動license sever就可以了。
Design Compiler
The Instry-Leading Synthesis Solution Is Now Even Better
Overview
Since 1988, Synopsys has focused on delivering state-of-the-art technologies such as gate-level synthesis, RTL synthesis, pre-verified DesignWare IP, integrated power & test optimization, advanced datapath optimizations, and physical synthesis, to provide you with the best tools that address your design needs--innovation is synonymous with Design Compiler.
The latest innovation is topographical technology in Design Compiler Ultra that enables designers to accurately predict post-layout timing and area ring RTL synthesis without the need for wireload model-based timing approximations. Created for RTL designers, Design Compiler Ultra with topographical technology requires no physical design expertise or changes to the synthesis use model. By accurately predicting post-layout timing and area, this solution eliminates costly iterations between synthesis and layout, providing faster time to results.
All of these advancements have resulted in a platform that delivers the fastest and smallest designs with lowest power and highest testability, now with the highest correlation to your back-end.
DC FLow
Key Benefits
* No need for wireload models (WLMs)
* Accurate prediction of post-layout timing and area
* Easy to adopt
Design Challenges
Increasing design complexity, shrinking geometries, higher clock speeds, and power rection/test compression requirements have become mainstream, making timing and area, correlation between synthesis and layout more challenging than ever. Larger synthesis block sizes coupled with shrinking geometries are driving net delays to be the dominant factor in path delays. Million-gate synthesis block sizes make it much harder to estimate the net capacitances based on statistical information. This results in timing and area correlation issues, where the results after RTL synthesis do not correlate to post-physical implementation results. The challenge is amplified even further since place & route solutions cannot compensate for a bad start point handed to them from synthesis.
Solution
Topographical technology, the latest innovation in synthesis, delivers accurate correlation to post-layout timing and area, without wireload models. It is designed for RTL designers and requires no physical design expertise or changes to the synthesis use model. The accurate prediction of layout timing and area in Design Compiler Ultra is achieved through the innovative 搕opographical technology�. It enables RTL designers to fix real design issues while still in synthesis and generate a better start point for physical design, eliminating costly iterations. Topographical technology shares technology with Galaxy physical design ensuring a smooth, convergent path from RTL to GDSII.
As part of the Galaxy Design Platform, the optimal design creation solution in the instry, you benefit from the following:
* Best-in-class optimization with DC Ultra
* No need for wireload models with topographical technology
* Proction-proven Test handoff with DFT Compiler and TetraMAX
* A complete power management solution with Power Compiler
* Instry-standard timing sign-off with PrimeTime
* The instry抯 largest IP repository with DesignWare
Related Procts
* DFT Compiler
* DesignWare IP
* Formality
* IC Compiler
* Leda
* Physical Compiler
* Power Compiler
* PrimeTime
* System Verilog
* VCS
* Vera